Research Area | Publications |
Auto-Vectorization |
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[CGO'19] Super-Node SLP: Optimized Vectorization for Code Sequences Containing Operators and Their Inverse Elements
Vasileios Porpodas, Rodrigo C. O. Rocha, Evgueni Brevnov, Luís F. W. Góes, Timothy Mattson.
Intl. Symp. on Code Generation and Optimization (CGO), Feb 2019.
pdf
bib
slides
LLVM Patch
Poster@EuroLLVM'19
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[LCPC'19] PostSLP: Cross-Region Vectorization of Fully or Partially Vectorized Code
Vasileios Porpodas and Pushkar Ratnalikar.
Intl. Wksp. on Languages and Compilers for Parallel Computing (LCPC), Oct 2019.
pdf
bib
slides
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[PACT'18] VW-SLP: Auto-Vectorization with Adaptive Vector Width
Vasileios Porpodas, Rodrigo C. O. Rocha and Luís F. W. Góes.
Intl. Conference on Parallel Architectures and Compilation Techniques (PACT), Nov 2018.
pdf
bib
slides
demo
video(LLVM-DEV'18)
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[CGO'18] Look-Ahead SLP: Auto-Vectorization in the Presence of Commutative Operations
Vasileios Porpodas, Rodrigo C. O. Rocha and Luís F. W. Góes.
Intl. Symp. on Code Generation and Optimization (CGO), Feb 2018.
pdf
bib
slides
LLVM SLP Patch
VPlan Patch (third-party)
Video@EuroLLVM'18
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[PACT'17] SuperGraph SLP Auto-Vectorization.
Vasileios Porpodas.
Intl. Conference on Parallel Architectures and Compilation Techniques (PACT), Sep 2017.
pdf
bib
slides
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[PACT'15] Throttling Automatic Vectorization: When Less Is More.
Vasileios Porpodas, and Timothy M. Jones.
Intl. Conference on Parallel Architectures and Compilation Techniques (PACT), Oct 2015.
pdf
bib
slides
LLVM patch (third-party)
video(LLVM'15)
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[CGO'15] PSLP: Padded SLP Automatic Vectorization.
Vasileios Porpodas, Alberto Magni and Timothy M. Jones.
Intl. Symp. on Code Generation and Optimization (CGO), Feb 2015.
pdf
bib
slides
video(EuroLLVM'15)
award@SCOPES'15
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Scalar Optimizations |
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Parallel Data Structures |
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Instruction Scheduling |
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Fault Tolerance |
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HW / Architecture |
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[HPCA'12] Cooperative Partitioning: Energy-Efficient Cache Partitioning for High-Performance CMPs.
Karthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones, Nigel P. Topham and Björn Franke.
Intl. Symp. on High-Performance Computer Architecture (HPCA), February 2012.
pdf
bib
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[JSPS] Decoupled Processors Architecture for Accelerating Data Intensive Applications using Scratch-Pad Memory Hierarchy.
A. Milidonis, N. Alachiotis, V. Porpodas, H. Michail, G. Panagiotakopoulos, A.P. Kakarountas, and C.E. Goutis.
Journal of Signal Processing Systems (JSPS), pages 1-16, 2009.
bib
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[CDT] Low-power architecture with scratch-pad memory for accelerating embedded applications with run-time reuse.
A. Milidonis, V. Porpodas, N. Alachiotis, A.P. Kakarountas, H. Michail, G. Panagiotakopoulos, and CE Goutis.
IET Computers & Digital Techniques (CDT) pages 109-123, 2009.
bib
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[VLSI-SOC'08] A Scratch-Pad Memory Accelerator for Exploiting Run-Time Reuse.
A. Milidonis, V. Porpodas, H. Michail, A.P. Kakarountas, G. Panagiotakopoulos and CE Goutis.
VLSI-SOC 2008.
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[DATE'07] A Decoupled Architecture of Processors with Scratch-Pad Memory Hierarchy.
A. Milidonis, N. Alachiotis, V. Porpodas, H. Michail, AP Kakarountas, and CE Goutis.
Design, Automation & Test in Europe (DATE), pages 1-6, 2007.
bib
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